1. Field of the Invention
The present invention relates to simulation of an aerial image, and particularly relates to simulation of an aerial image produced by a mask to be used in patterning an integrated circuit (IC) chip during semiconductor wafer fabrication.
2. Description of the Related Art
A. Wafer Construction
Photolithography is a common technique employed in the manufacture of semiconductor devices. Typically, a semiconductor wafer is coated with a layer (film) of light-sensitive material, such as photoresist. Using a patterned mask or reticle, the wafer is exposed to projected light, typically actinic light, which manifests a photochemical effect on the photoresist, which is subsequently chemically etched, leaving a pattern of photoresist "lines" on the wafer corresponding to the pattern on the mask.
A "wafer" is a thin piece of semiconductor material from which semiconductor chips are made. The four basic operations utilized to fabricate wafers include (1) layering, (2) patterning, (3) doping and (4) heat treatments.
The layering operation adds thin layers of material, including insulators, semiconductors, and conductors, to a wafer surface. During the layering operation, layers are either grown or deposited. Oxidation involves growing a silicon dioxide (an insulator) layer on a silicon wafer. Deposition techniques include, for example, chemical vapor deposition, evaporation, and sputtering. Semiconductors are generally deposited by chemical vapor deposition, while conductors are generally deposited with evaporation or sputtering.
Patterning involves the removal of selected portions of surface layers. After material is removed, the wafer surface has a pattern. The material removed may form a hole or an island. The process of patterning is also known to those skilled in the relevant art as microlithography, photolithography, photomasking and masking. The patterning operation serves to create parts of the semiconductor device on the wafer surface in the dimensions required by the circuit design and to locate the parts in their proper location on the wafer surface.
Doping involves implanting dopants in the surface of the wafer through openings in the layers to create the n-type and p-type pockets needed to form the N-P junctions for operation of discrete elements such as transistors and diodes. Doping is generally achieved with thermal diffusion (the wafer is heated and exposed to the desired dopant) and ion implantation (dopant atoms are ionized, accelerated to high velocities and implanted into the wafer surface).
Construction of semiconductor wafers with these steps is well known in the art of semiconductor fabrication. Examples of wafer construction processes are described in U.S. Pat. No. 5,679,598 issued to Yee on Oct. 21, 1997, entitled "Method of Making a CMOS Dynamic Random-Access Memory (DRAM)," U.S. Pat. No. 5,663,076 issued to Rostoker et al. on Sep. 2, 1997, entitled "Automating Photolithography in the Fabrication of Integrated Circuits," U.S. Pat. No. 5,595,861 issued to Garza on Jan. 21, 1997, entitled "Method of Selecting and Applying a Top Antireflective Coating of a Partially Fluorinated Compound," U.S. Pat. No. 5,444,265 issued to Hamilton on Aug. 22, 1995, entitled "Method and Apparatus for Detecting Defective Semiconductor Wafers During Fabrication Thereof," and U.S. Pat. No. 4,652,134 issued to Pasch et al. on Mar. 24, 1987, entitled "Mask Alignment System." The specifications of these five patents identified in this paragraph are hereby incorporated herein as though set forth in full by this reference.
B. Patterning And Proximity Effects
One of the most critical operations in wafer fabrication, patterning sets the dimensions of the electronic devices to be implemented on the IC chip. Errors in the patterning process can cause distortions that cause changes in the functions of these electronic devices.
Design rule limitations frequently are referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Consequently, the critical dimension determines the overall size and density of an IC. In present IC technology, the smallest critical dimension for state-of-the-art circuits is 0.3 micron for line widths and spacings.
Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit is to transfer the layout onto a semiconductor substrate. Photolithography is a well known process for transferring geometric shapes present on a mask onto the surface of a silicon wafer. In the field of IC lithographic processing, a photosensitive polymer film called photoresist is normally applied to a silicon substrate wafer and then allowed to dry. An exposure tool is utilized to expose the wafer with the proper geometrical patterns through a mask (or reticle) by means of a source of light or radiation. After exposure, the wafer is treated to develop the mask images transferred to the photosensitive material. These masking patterns are then used to create the device features of the circuit.
FIG. 1A is a functional block diagram illustrating a system for patterning an IC chip 26 using a mask 22. Referring to FIG. 1, light 21 is incident on mask 22 at a right angle. Such would be the case for a single point light source directly above mask 22 and far enough from mask 22 so that the wavefront at mask 22 would be approximately planar. It should, however, be noted that light 21 is shown in this manner for illustration purposes only. Generally, the light source will be an extended body consisting of many different points and, accordingly, light generally will strike mask 22 at many different angles. Thus, as shown in FIG. 1B, the light from points 31 and 32 on light source 30 will strike mask 35 at different angles.
Mask 22 includes transmissive and non-transmissive portions which effectively transmit and block light 21 so as to produce the desired pattern on IC chip 26. The light 23 exiting from mask 22 passes through optical system 24 and, finally, contacts IC chip 26, forming a light intensity pattern. Often, optical system 24 merely comprises the distance between mask 22 and IC chip 26. However, optical system 24 may include one or more lenses, mirrors and/or other optical elements.
An important limiting characteristic of the exposure tool is its resolution value. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose onto the wafer. Currently, the resolution for most advanced optical exposure tools is around 0.2 micron. Thus, the resolution value of present lithographic equipment is close to the critical dimension for most IC circuit designs. Consequently, the resolution of the exposure tool may influence the final size and density of the IC circuit. As the critical dimensions of the layout become smaller and approach the resolution value of the lithographic equipment, the consistency between the masked and actual layout pattern developed in the photoresist is significantly reduced. Specifically, it is observed that differences in pattern development of circuit features depends upon the proximity of the features to one another.
The magnitude of such proximity effects depends on the proximity or closeness of the two features present on the masking pattern. Proximity effects are known to result from optical diffraction in the projection system. This diffraction causes adjacent features to interact with one another in such a way as to produce pattern-dependent variations.
Proximity effects and methods for correcting for them (i.e., optical proximity correction, or OPC, methods) are discussed in U.S. Pat. No. 5,682,323 issued on Oct. 28, 1997, to Pasch et al. entitled "System and Method for Performing Optical Proximity Correction on Macrocell Libraries" (hereinafter the "Pasch '323 patent"). The specification of the Pasch '323 patent is incorporated herein as though set forth in full by this reference. The system and method described in the Pasch '323 patent performs optical proximity correction on an integrated circuit mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. An optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.
Proximity effects and methods for correcting for them are also discussed in U.S. Pat. No. 5,705,301 issued on Jan. 6, 1998, to Garza et al. entitled "Performing Optical Proximity Correction with the Aid of Design Rule Checkers" (hereinafter the "Garza '301 patent"). The specification of the Garza '301 patent is incorporated herein as though set forth in full by this reference. The system described in the Garza '301 patent involves a method for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only.
More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.
C. Mask Design
An overview of a technique for designing a mask will now be described with reference to the flow diagram shown in FIG. 2. Referring to FIG. 2, in step 42 an initial mask pattern is obtained. Generally, points in the initial mask pattern will have an amplitude of one where the pattern is supposed to appear on the chip and an amplitude of zero where no pattern is to appear on the chip. However, the initial mask pattern instead may be specified in other ways.
In step 44, an aerial image which would be produced by a mask having the mask pattern is simulated. Examples of conventional techniques for simulating an aerial image are described below.
In step 46, it is determined whether the simulated image is acceptable. Generally, the main criterion in making this determination is whether the simulated image has sufficient resolution to enable patterning which will result in error-free device fabrication. If the image is acceptable, then processing proceeds to step 48 in order to fabricate a mask having the designed pattern. Otherwise, processing proceeds to step 52.
In step 52, the mask pattern is altered, such as by adding and/or modifying serifs, in an attempt to improve the resolution of the aerial image. Such a process is described in more detail below. Upon completion of mask pattern alteration, processing returns to step 44 in order to simulate an aerial image based on the new mask pattern.
D. Proximity Effect Correction
A technique related to proximity effects involves the use of modified shapes or adjacent subresolution geometries to improve imaging. An example of this is the use of serifs on the corners of contacts. For contacts with dimensions near the resolution limit of the optics, a square pattern on the reticle will print more nearly as a circle. Additional geometries on the corners will help to square the corners of the contract. Such techniques often are called proximity correction. An example of such a technique is described in U.S. patent application Ser. No. 09/034,550 filed Mar. 3, 1998 and titled "Method And Apparatus For Application Of Proximity Correction With Relative Segmentation," which application is incorporated by reference herein as though set forth herein in full.
Proximity effects are a well-known phenomenon in electron beam lithography, where they result from electron scattering. In optical lithography proximity effects are caused by the phenomenon of diffraction. As a consequence of proximity effects, printed features do not have simple relationships to reticle dimensions. This creates a situation in which it is difficult to fabricate a photomask where the designer gets what he or she wants on the wafer.
Some limited form of proximity correction has been in use for at least two or three decades. These pattern modifications were usually requested by a wafer engineer based on knowledge of a particular process step. In recent years, proximity correction has become more of a science than an art due to the introduction of several proximity correction software programs. The proximity correction process consists of measuring several generic test patterns processed on a wafer and constructing a multilevel lookup table from the measured data.
E. Numerical Simulation of an Aerial Image
Lithographic simulators are becoming an important tool in the evaluation of optimal lithographic processing. Specifically, by simulating aerial images, the time required to design a mask often can be shortened. Simulators often are also useful for correcting optical proximity effects.
The aerial image produced by a mask, or the light intensity in an optical projection system's image plane, is a critically important quantity in microlithography a for governing how well a developed photoresist structure replicates a mask design. The aerial image represents, to a large extent, the optical information about the mask that enters into the photoresist structure. Of course, the full calculation of the resist structure generally has to take into account other factors, such as propagation of light within the resist, exposure of the resist, any subsequent thermal or other such processes, and the dissolution of the resist. Nevertheless, the aerial image typically is the single most important predictor of mask printability.
The models used in conventional aerial image simulators are based either on scalar diffraction theory or vector diffraction theory. The models based on scalar theory usually follow the analysis of Hopkins. In Hopkins's analysis, light intensity is propagated through the optical system. The mask plane is treated as a partially coherent source surface, and a coherent transfer function describes how a point source in the mask plane is imaged in the plane of the resist. The aerial image (light intensity) at a point r.sub.p is given as: EQU I(r.sub.p)=.intg..intg..intg..intg.U(r.sub.m1)U(r.sub.m2)K(r.sub.m1,r.sub. p)K(r.sub.m2,r.sub.p)B(r.sub.m1,r.sub.m2)dr.sub.m1 dr.sub.m2 (1)
where r.sub.m1 and r.sub.m2 are points in the mask plane; K(r.sub.m1,r.sub.p) is the coherent impulse response function of the optical system; U(r.sub.m1) is the mask complex transmission function; and B(r.sub.m1,r.sub.m2) is the mutual coherence function of the light at the mask plane.
If expression (1) is used for calculation of an aerial image at point r.sub.p, the number of operations required generally is on the order of L.sup.2, where L is the number of points in the region of integration. It is noted that L generally determines the accuracy of the numerical integration of the integral in equation (1). In order to calculate the aerial image at a mesh with N nodes, the number of operations required generally is on the order of NL.sup.2. Frequently, L is of the same order as N.
The second group of models (i.e., those based on vector diffraction theory) generally follow the work of Yeung, who traces vector electric fields through the optical system onto the photoresist surface. Specifically, each ray emanates from a particular source point and travels through a different portion of the mask and the optical system. One advantage of this method is the possibility of application of the Fast Fourier Transform (FFT) in the calculation of coherent images from each source point. The electric field at the resist surface due to that source point can be obtained by integration over the solid angles subtended by the optical system, and may be represented as: ##EQU1##
is the Fourier transform of the mask transmission function, H(.rho.) is the coherent transmission function of the optical system, I(r.sub.u) is the intensity distribution at the source surface, and I.sub.0 is the open frame intensity.
The aerial image calculation according to equation (2) thus consists of the following steps: (1) find the Fourier transform of the mask transmission function, which is called the spatial frequency spectrum of the mask; (2) multiply the spatial frequency spectrum of the mask by the coherent transmission function of the optical system, and repeat this step for each source point used in the calculation of the aerial image; (3) find the inverse Fourier transform of the function obtained in step (2); (4) multiply the result obtained in step (3) by its complex conjugate value; and (5) sum the coherent aerial images from all source points.
Steps (1) and (3) may be executed with the FFT algorithm. This calculation generally is the fastest way of obtaining the aerial image at a mesh having N nodes, because it typically only requires on the order of P(N+1)IgN operations, where P is the number of source points and typically is much smaller than N.
A variety of simulators are commercially available. Probably the most popular is Fast Aerial Image Model (FAIM), developed by Vector Technologies, Inc. and Princeton University. FAIM is capable of simulating segments of a computer-aided design (CAD) layout. It is generally uniform in accuracy and enables the user to simulate an aerial image of a segment (4.times.12 microns) in about 12 seconds on a 20 MFLOPS workstation.
As noted above, aerial image simulators are very important in OPC. In these applications, the simulator is required to be very fast because it is in a loop for performing an iterative correction procedure. Accordingly, improvements in the speed of such simulators are highly desirable, particularly when such simulators are used in OPC.
As noted above, Yeung's technique is relatively fast, because it can be executed using the FFT algorithm. However, Yeung's technique typically introduces additional errors into the simulation process. Specifically, prior to determining the FFT in step (1) above, the mask transmission function generally must first be rasterized. In this regard, the mask transmission function typically is initially represented in GDS2 format, which provides a geometric description of the mask pattern. Transformation into raster format is accomplished by sampling the mask pattern on a rectangular mesh. However, the mask transmission function generally is not analytical near polygon boundaries, and therefore the GDS2-to-raster transformation often introduces errors. In general, these areas become larger as the polygon dimensions become smaller.
An example of such errors is illustrated with reference to FIGS. 3A and 3B. Specifically, FIG. 3A illustrates a mask pattern 71 superimposed over a mesh 72. Mesh 72 includes regularly spaced nodes, such as nodes 74. Generally, rasterization is performed by determining whether a node is more or less than 50 percent occupied by transmissive portions of the mask pattern. If a particular node is more than 50 percent occupied by transmissive portions, the entire node is represented as transmissive. Otherwise, the entire node is represented as non-transmissive. Thus, FIG. 3B illustrates a pattern 78 which results after rasterizing mask pattern 71. As seen by comparing FIGS. 3B and 3A, several errors have occurred during rasterization. In particular, pattern 78 is shifted to the left and upward as compared to pattern 74. In addition, the entire triangular portion 79 of pattern 74 has been eliminated in pattern 78.
The effects of rasterization error can be reduced by using a finer rasterization mesh. However, using a finer mesh also significantly increases the complexity of the required calculations by increasing the number of required operations. Thus, the conventional techniques typically require a trade-off between speed and accuracy.
What is needed, therefore, is a technique for aerial image simulation which can maintain high accuracy and which can be executed very quickly.